1) Field of the Invention
This invention relates generally to the fabrication of capacitors in a DRAM cell and particularly to a method for fabricating capacitors over bit lines with large capacitance and more particularly to a method for fabricating a crown cylindrical capacitor.
2) Description of the Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrates are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
The following U.S. patents show related processes and capacitor structures: U.S. Pat. No. 5,543,345 (Liaw et al.), U.S. Pat. No. 5,550,076 (Chen), U.S. Pat. No. 5,604,146 (Tseng), and U.S. Pat. No. 5,491,103 (Ahn et al.). U.S. Pat. No. 5,545,584 (Wuu et al.) shows a unified contact plug process. However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly.
There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method that minimizes the number of photoresist masking operations and to provide maximum process tolerance to maximize product yields. There is also a challenge to develop a capacitor which is not limited in size by the photolithographic techniques.